Column-matching Based Mixed-mode Bist Technique

A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan circuits, together with necessary supplementary algorithms, is proposed in this Thesis. This method is mostly based on a design of a combinational block the Decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by some ATPG tool. The Column-Matching algorithm to design the decoder is proposed. Here the maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns, which reduces the BIST area overhead. Since quite a large number of test vectors is often needed to sufficiently test a particular circuit, synthesizing all these vectors deterministically would involve a very large area overhead. Thus, the basic Column-Matching method has been extended to support the mixed-mode testing. Here the BIST execution is divided into two disjoint phases – the pseudo-random phase, where the pseudo-random patterns are being applied to the circuit unmodified, and the deterministic phase detecting all the yet undetected faults. This enables us to reach high fault coverage in a short test time and with a low area overhead. The novelty of this approach comprises of the fact that these phases are disjoint. As a consequence of this, the BIST control logic is significantly reduced, when compared to other state-of-the-art methods. The choice of the lengths of the two phases directly influences the test time, BIST design time and BIST area overhead. The Column-Matching algorithm is described in details in the Thesis and several heuristic methods solving some of the major NP-hard problems involved are proposed. The tradeoff between the duration of the execution of BIST, the solution quality and runtime is discussed. The time complexity of the algorithm is studied and experimentally evaluated. A truth table description of a Boolean function is obtained as a result of the Column-Matching algorithm. This function describes the Output Decoder logic. In order to maximally reduce the BIST area overhead, the function has to be minimized. Since it is usually a function of many input and output variables (hundreds, thousands), available Boolean minimizers were not able to handle it in a reasonable time. Thus, an efficient Boolean minimizer has been developed for this reason. BOOM, as a minimizer capable to process functions having many input variables, is proposed. The implicants of a function are generated by a top-down way: the universal hypercube is being gradually reduced, until it becomes an implicant. This approach becomes very advantageous for sparse functions, i.e., functions where values of only few minterms are defined. This is exactly the case of the Column-Matching BIST design. The efficiency of Boom for such functions is documented on standard benchmark circuit, as well as on practical Column-Matching examples. The proposed BIST design method was tested on ISCAS and ITC’99 benchmarks and the results were compared with the results obtained by some of the state-of-the-art methods. The complete resulting BIST equipment logic was synthesized and its complexity evaluated. A complete (100%) stuck-at fault coverage was considered in all the experiments performed. The main contributions of this Thesis are the following: • A new BIST design methodology is proposed • The BIST process is divided into two separate phases, unlike in other methods • A new and very efficient Boolean minimizer is proposed